Embedded copper features within dielectric substrates find widespread use for various electronic applications. For example, integrated circuits of microprocessors generally include numerous levels of interconnect routing in the form of copper interconnects, such as lines and dots, embedded within a dielectric substrate to connect transistors within the integrated circuits. Each level of interconnect routing is separated from immediately adjacent levels by the dielectric material, referred to in the art as an interlayer dielectric (ILD). Adjacent levels of interconnect routing may be embedded in distinct layers of ILD, and with the interconnect routing configured in such a way so as to ensure that dielectric material separates the adjacent interconnect routings. In this regard, the embedded copper interconnects in the interconnect routing can be selectively insulated from both other embedded copper interconnects in the same interconnect routing and from embedded copper interconnects in interconnect routing of adjacent levels. Likewise, embedded copper interconnects in adjacent levels of interconnect routing can also be selectively connected to fabricate desired circuitry in the integrated circuits.
With advances in integrated circuits, driven by a desire to shrink sizes, aspect ratios of height to width of the embedded copper interconnects in the interconnect routing have been maximized to enable spacing between the embedded copper interconnects to be minimized. However, the minimized spacing between the embedded copper interconnects gives rise to device reliability concerns that are attributable to various phenomena. One particular phenomena that gives rise to reliability concerns is time dependent dielectric breakdown (TDDB), which results from migration of copper ions from the embedded copper interconnects into an interface between adjacent levels of the interconnect routing. TDDB is often exacerbated with decreased spacing between embedded copper interconnects in the interconnect routings. To combat TDDB, efforts have been made to recess the embedded copper interconnects within the ILD, thereby offsetting surfaces of the embedded copper interconnects from a plane of the interface between the adjacent levels and effectively forming a barrier to flow of copper ions into the interface. In particular, during formation of the levels of interconnect routing, a layer of ILD may be formed upon a substrate, which may be a semiconductor substrate or another level of interconnect routing. Trenches and/or vias may be etched into the ILD, followed by deposition of copper into the trenches and/or vias. Excess copper may be removed through chemical and/or mechanical removal techniques to define the interconnect routing of embedded copper interconnects. Wet etch techniques are then employed to etch copper from the exposed surfaces of the embedded copper interconnects to thereby recess the embedded copper interconnects within the ILD prior to forming additional layers thereon.
Unfortunately, existing processes for recessing embedded copper interconnects within ILD also give rise to reliability concerns. In particular, wet etch techniques for etching copper from the exposed surfaces of the embedded copper interconnects result in an uneven topography in the recessed surfaces of the embedded copper interconnects and impacts formation of additional layers upon the embedded copper interconnects after recessing. Plasma-enhanced chemical vapor deposition (PECVD) is often used to form the additional layers over the embedded copper interconnects after recessing. Because layers formed through PECVD are generally not highly conformal, gaps may be formed between the recessed surfaces of the embedded copper interconnects and the additional layers formed thereon through PECVD, due to the uneven topography in the recessed surfaces of the embedded copper interconnects. The presence of such gaps between the recessed surfaces of the embedded copper interconnects and the additional layers formed thereon may give rise to device reliability concerns. Gap formation may even be a concern if a highly conformal layer is formed over the embedded copper interconnects after recessing due to the uneven topography in the recessed surfaces of the embedded copper interconnects after recessing.
Accordingly, there is a need to provide processes for recessing copper features within a substrate that promote formation of topography of maximized evenness in the recessed surface of the embedded copper features. In particular, there is a need to provide processes for recessing an embedded copper interconnect within an interlayer dielectric substrate in an integrated circuit, with the embedded copper interconnect having a recessed surface of maximized evenness. There is also a need to provide integrated circuits having an interlayer dielectric substrate with an embedded copper interconnect recessed therein and having a recessed surface, and with the recessed surface of the embedded copper interconnect having topography of maximized evenness.